The Vitis core development kit calls the Vivado Design Suite during the linking process to automatically run RTL synthesis and implementation when generating the FPGA binary (.xclbin). You also have the option of launching the Vivado tool directly from within the Vitis IDE to interact with the project for synthesizing and implementing the FPGA binary. There are three commands to support interacting with the Vivado tool from the Vitis IDE, accessed through the menu:
hw_linkproject must be opened and be the current project in the IDE for these options to be available.
- Open Vivado Project
- This automatically opens the Vivado project (.xpr) associated with the Hardware build
configuration. In order for this feature to work, you must have previously
completed the Hardware build so that a Vivado project exists for the build.
Opening the Vivado project launches the Vivado IDE and opens the implementation design checkpoint (DCP) file to edit the project, to let you manage the results of synthesis and implementation more directly. You can then use the results of this effort for generating the FPGA binary by selecting Import Design Checkpoint.
- Import Design Checkpoint
- Lets you specify a Vivado DCP file to use as the basis for the Hardware build, and for generating the FPGA binary.
- Import Vivado Settings
- Lets you specify a configuration file used by the Vivado tools, as described in Vitis Compiler Configuration File, for use during the linking process.
Using the Vivado IDE in standalone mode enables the exploration of various synthesis and implementation options for further optimizing the kernel for performance and area. There are additional options available to let you interact with the FPGA build process. See Managing Vivado Synthesis and Implementation Results for more information.
v++ --configfile options. Fore more information, refer to v++ Command.