Mailbox Semantics - 2022.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
Release Date
2022-12-07
Version
2022.2 English

The mailbox features can be used for both input and output, and would need to be specified for all s_axilite I/Os of an HLS design. It is enabled with a global option for the interfaces using the Vitis HLS config_interface command:

config_interface -s_axilite_mailbox both
config_interface -s_axilite_auto_restart_counter 1

After setting up the config_interface option, the mailbox implements a pair of registers called HW copy and SW copy. The input mailbox and output mailbox has an independent pair of registers as shown in the below figure. Communication from the software application with the HLS design includes:

Input Mailbox
  • The application writes some or all elements to the SW copy register of the mailbox.
  • The application notifies the mailbox that SW copy is updated.
  • When the HLS design restarts, the SW copy register is copied to the HW copy register.
  • The application is notified that the HW copy has been updated, and can change the SW copy register again as needed.
    Tip: Multiple reads by the HLS design can occur without an update from the software application.
Output Mailbox
  • The application notifies the mailbox that it wants to read an updated copy of the mailbox. The HLS design writes some or all the elements to the HW copy register of the mailbox at the end of the current execution.
  • When the design is done, HW copy is copied to the SW copy register.
  • The application is notified that SW copy is updated and can read it at any time.
    Tip: Multiple writes by the hardware can occur without any software request to update.