To synthesize the active solution of the project, select the Run C Synthesis command in the Flow Navigator, or select the command on the toolbar menu.
The C/C++ source code is synthesized into an RTL implementation. During the synthesis process messages are transcripted to the console window, and to the vitis_hls.log file.
INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 4, Depth = 6. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 19.38 seconds; current allocated memory: 397.747 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.57 seconds; current allocated memory: 400.218 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'dct'
Within the Vitis™ HLS IDE, some messages contain links to additional information. The links are highlighted in blue underlined text, and open help messages, source code files, or documents with additional information in some cases. Clicking the messages provides more details on why the message was issued and possible resolutions.
When synthesis completes, the Simplified Synthesis report for the top-level function opens automatically in the information pane as shown in the following figure.
You can quickly review the performance metrics displayed in the Simplified Synthesis report to determine if the design meets your requirements. The synthesis report contains information on the following performance metrics:
- Issue Type
- Shows any issues with the results.
- Number of clock cycles required for the function to compute all output values.
- Initiation interval (II)
- Number of clock cycles before the function can accept new input data.
- Loop iteration latency
- Number of clock cycles it takes to complete one iteration of the loop.
- Loop iteration interval
- Number of clock cycles before the next iteration of the loop starts to process data.
- Loop latency
- Number of cycles to execute all iterations of the loop.
- Resource Utilization
- Amount of hardware resources required to implement the design based on the resources available in the FPGA, including look-up tables (LUT), registers, block RAMs, and DSP blocks.
If you specified the Run C Synthesis command on multiple solutions, the Console view reports the synthesis transcript for each of the solutions as they are synthesized. After synthesis has completed, instead of the Simplified Synthesis report, Vitis HLS displays a Report Comparison to compare the synthesis results for all of the synthesized solutions. A portion of this report is shown below.