create_testbench - 2022.2 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

Document ID

UG835

Release Date

2022-10-19

Version

2022.2 English

Create testbench for design unit instance

Syntax

create_testbench [‑name <arg>] [‑mode <arg>] [‑type <arg>]
    [‑add_to_simset <arg>] [‑runtime <arg>] [‑set_as_top] [‑force] [‑quiet]
    [‑verbose]

Usage

Name	Description
`[-name]`	Name of the testbench module Default: testbench
`[-mode]`	Simulation mode (behavioral, post-synthesis or post-implementation) Default: behavioral
`[-type]`	Netlist type (functional or timing)
`[-add_to_simset]`	Add the generated testbench to the specified simulation fileset
`[-runtime]`	Set simulation runtime
`[-set_as_top]`	Set generated testbench module as top
`[-force]`	Overwrite existing testbench source file
`[-quiet]`	Ignore command errors
`[-verbose]`	Suspend message limits during command execution

Description

Create testbench for a design unit instance. This command will create a functional system verilog based testbench for the scoped hierarchical instance. The testbench contains port/signal specification, parameter declaration, stimuli vector include file, and module instantiation of the selected instance as DUT (Design Under Test).

The command allows user to add the testbench to an existing or a new simulation fileset from which the simulation can be launched.

Note: The generated testbench is simulator independent.

Arguments

-name <arg> - (Optional) Specify the name of the testbench module name. Default name is testbench.

-add_to_simset <arg> - (Optional) Specify name of the simulation fileset to which the testbench needs to be added. If this switch is not specified then the command will add the testbench to currect active simulation fileset.

-set_as_top - (Optional) Set the generated testbench module as top in the simulation fileset where the testbench will be added.

-mode <arg> - (Optional) Specifies simulation mode. Allowed values are: behavioral, port-synthesis, or post-implementation. Default is behavioral.

-type <arg> - (Optional) Specifies simulation type. Allowed values are: functional or timing (not applicable for behavioral mode).

-force - (Optional) Overwrite existing testbench file.

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.

Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.

-verbose - (Optional) Temporarily override any message limits and return all messages from this command.

Note: Message limits can be defined with the set_msg_config command.

Examples

The following command will create a testbench for module fifo and add it to the sub_design_fifo simulation fileset:

create_testbench -name fifo -add_to_simset sub_design_fifo

The following commands will generate VCD file for /top/DUT/fifo/buf_1 instance of type buf module, record the waveform activity in VCD file for 2000ns, create a testbench with module named tb, add the testbench to the test_buffer simulation fileset and set tb as top module in this fileset:

generate_vcd_ports {/top/DUT/fifo/buf_1}
    run 2000ns
    close_vcd -ports
    create_testbench -name tb -add_to_simset test_buffer -set_as_top