The Netlist window (shown in the following figure) provides a hierarchical view of the elaborated or synthesized logic design including the nets, logic primitives, and hierarchical modules of the design, starting with the currently defined top module. To open the Netlist window, select .
The Netlist window includes the following folders:
- Leaf Cells
- Displays primitive logic for each level of the hierarchy. This folder condenses the display of logic content and hierarchical modules in the Netlist window (shown in the following figure).
- Displays nets, or wires, for each level of the hierarchy. All of the bits of a bus are collapsed under the bus by default, but you can expand buses to show each individual bit (shown in the following figure).