The Vitis™ High-Level Synthesis (HLS) tool transforms a C specification into a register transfer level (RTL) implementation that you can synthesize into a Xilinx device. You can write C specifications in C, C++, or SystemC, and the Xilinx device provides a massively parallel architecture with benefits in performance, cost, and power over traditional processors.
The outputs from Vitis HLS include RTL implementation files in hardware description language (HDL) formats that can be synthesized in Vivado synthesis or packaged as an IP block for use from the IP catalog. For more information, see Vitis High-Level Synthesis User Guide (UG1399).