You can increase margin in SSN analysis by adding phase information. By default, SSN analysis assumes that every output port toggles synchronously. This assumption covers the worst-case scenario that often yields an overly pessimistic SSN Analysis report. If clock information for the design is available, SSN analysis reports more accurate SSN noise.
To use this feature, enable SSN phase analysis using the following Tcl command:
Enter clocking information using the
create_generated_clock Tcl commands. These commands provide the
following required inputs to SSN analysis:
- Phase groupNote: This groups generated clocks that belong to a single MMCM or PLL.
- Duty cycle
- Phase shiftNote: This covers an absolute phase shift from zero degrees.
Following are important considerations:
- Multiple master clocks do not improve SSN results. There must be multiple phases within each master clock to reduce SSN results.
- A single port within a phase group does not improve SSN results. For each clock group or phase group, there must be at least two ports.
To minimize SSN noise, shift the clock transitions of one clock with respect to another clock, for both clock signals in same phase-group as well as clock signals in different phase-groups. The magnitude (in ps) of these shifts are design and architecture dependent.
Following are additional considerations:
- For large designs, running SSN analysis with phase support might take in the tens of minutes.
- Shifting 180 degrees does not improve SSN results. Although clocking information includes rising and falling transition information, SSN analysis does not include actual output logic of the ports. When a clock transitions from Low to High, the output of a port can go in either direction. To ensure conservative SSN reporting, the algorithm assumes 180 degrees is the same as zero phase shift. Due to the lack of information on the output ports, the analysis overestimates SSN noise for ports with 180 degree shift. In reality, the SSN actual reduces with a 180 degree shift, but the algorithm cannot account for the reduction.
- Only 50% duty cycle is supported, and non-conforming clocks are considered as asynchronous signals.