Navigating Content by Design Process - 2022.2 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)
Document ID
UG899
Release Date
2022-10-19
Version
2022.2 English

Xilinx® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. All Versal® ACAP design process Design Hubs and the Design Flow Assistant materials can be found on the Xilinx.com website. This document covers the following design processes:

System and Solution Planning
Identifying the components, performance, I/O, and data transfer requirements at a system level. Includes application mapping for the solution to PS, PL, and AI Engine.

The following table summarizes various interface speed options available in each architecture for easy document navigation. Note that the bit-rates mentioned in the table are based on hardware characterization using LVDS in speed grade -3 devices.

Table 1. Navigating IP and Clock Planning Content
Device Architecture Additional Considerations Relevant Links
7 series HRIO (Low Speed I/O)
  • Bit-rate range 0 to 1250 Mb/s
HPIO (High Speed I/O)
  • Bit-rate range 0 to 1600 Mb/s
UltraScale/UltraScale+ Component Mode (Low Speed I/O)
  • Bit-rate range for UltraScale HP/HR bank or UltraScale+ HP bank 0-1250 Mb/s
  • Bit-rate range for UltraScale+ HD bank 0-250 Mb/s
Native Mode (High Speed I/O)
  • Bit-rate range 300 to 1600 Mb/s (only HP banks)
Versal ACAP I/O Logic (Low Speed I/O)
  • Bit-rate range 0-300 Mb/s (Both HD and XP banks)
XPIO (High Speed I/O)
  • Bit-rate range 200-1800 Mb/s (Only XP banks)