Working with SSN Analysis‌‌ - 2022.2 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

Document ID
UG899
Release Date
2022-10-19
Version
2022.2 English

The Vivado IDE provides analysis of the switching noise levels associated with the I/O of different devices. SSN analysis provides estimates of the disruption that simultaneously switching outputs can cause on other output ports in the I/O bank. SSN analysis incorporates I/O bank-specific electrical characteristics into the prediction to better model package effects on SSN.

I/Os are grouped into separate isolated I/O banks, and each I/O bank has unique power distribution networks and unique responses to switching activity. Because power distribution networks within a packaged FPGA have different responses to noise, it is important to understand the I/O standards and number of I/Os in a design as well as the response of the device power system to this switching.

Xilinx characterizes all banks through three-dimensional extraction and simulation. This information is incorporated into SSN analysis. SSN analysis uses the expected switching profile of a device to predict how the switching affects the power network of the system and in turn, how other outputs in the I/O bank are affected.

Note: SSN analysis analyzes output signals only, including the output of bidirectional ports, and ignores input signals in the calculation. As long as the I/O bank includes a sufficient margin, input and output levels are not affected.
Important: SSN analysis is the most accurate method available for predicting how output switching affects interface noise margins. The calculation and results are based on a range of variables. These estimates are intended to identify potential noise-related issues in your design and are not intended as final design sign-off criteria.