Vivado® Design Suite provides simulation models as a set of files and
libraries. Simulation libraries contain the device and IP behavioral and timing models.
The compiled libraries can be used by multiple design projects. You must compile these
files prior to design simulation through a utility called
compile_simlib to compile the simulation models for the target
simulator. This utility can be invoked from the Vivado IDE or by
executing it from the Tcl console.
For SystemC simulation verification, simulation models are provided in C/C++/SystemC. Vivado Design Suite provides two sets of simulation models:
- Protected models
- Unprotected models