Elaborated Design Constraints - 2022.2 English

At this point in the flow, the net delay modeling is still not very accurate. The main goal is to obtain a synthesized netlist which meets timing, or fail by a small amount, before starting implementation. In many cases, you will have to go through several XDC and RTL modification iterations before you can reach this state.

The RTL-based XDC creation iteration is shown in the following figure. It is based on the utilization of the Elaborated design to find the object names in your design that you want to constrain for synthesis.

You must use the Tcl Console to validate the syntax of the XDC commands before saving them in the XDC files. With the elaborated design, you can create constraints, query clocks, and query design objects, but you cannot run any timing report command.

Figure 1. Creating Constraints with the Elaborated Design

Design objects that are safe to use when writing constraints for synthesis are:

• Top level ports
• Manually instantiated primitives (cells and pins)

Some RTL names are modified or lost during the creation of the elaborated design. Following are the most common cases:

• Single-Bit Register Names
• Multi-Bit Register Names
• Absorbed Registers and Nets
• Hierarchical Names