Multicycles Between SLOW-to-FAST Clocks - 2022.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)
Document ID
UG903
Release Date
2022-11-02
Version
2022.2 English

In this scenario, the launch clock CLK1 is the slow clock; the capture clock CLK2 is the fast clock. See the following figure.

Figure 1. Multicycles Between SLOW-to-FAST Clocks

For example, assume the following:

  • CLK2 is three times the frequency of CLK1.
  • A clock enable signal on the receiving registers allows a Multicycle constraint to be set between both clocks. See the following figure.
Figure 2. Multicycles Between SLOW-to-FAST Clocks

The setup and hold relationships that are resolved by the STA tool when no multicycle is applied are shown in the following figure.

Figure 3. Default Setup and Hold Relationships