TIMING-32: Bus Skew Constraint Applied on Too Many Signals - 2022.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2022-10-19
Version
2022.2 English

The bus skew constraint is set on too many signals (> 2500 paths for UltraScale/UltraScale+ or 1000 paths for 7 series). See the constraint position <position> in the timing constraint window in the Vivado IDE. The first endpoint covered by the constraint is <object>.