The device configuration settings for the Artix UltraScale+,
devices available for use with the
<Setting> <Value> [current_design]
tool Tcl command are shown in the
|Setting||Default Values||Possible Values||Description|
|BITSTREAM. AUTHENTICATION. AUTHENTICATE||No||No, Yes||Indicates whether or not to use RSA authentication. If No then AES_GCM is used.|
|BITSTREAM. AUTHENTICATION. RSAPRIVATEKEYFILE||Specifies the OpenSSL .pem file that contains the key pairs that should be used to sign the RSA-2048 authenticated bitstream.|
|BITSTREAM.CONFIG. BPI_1ST_READ_CYCLE||1||1, 2, 3, 4||Helps synchronize BPI configuration with the timing of page mode operations in flash devices. It allows you to set the cycle number for a valid read of the first page. The BPI_page_size must be set to 4 or 8 for this option to be available.|
|BITSTREAM.CONFIG. BPI_PAGE_SIZE||1||1, 4, 8||For BPI configuration, this sub-option lets you specify the page size which corresponds to the number of reads required per page of flash memory.|
|BITSTREAM.CONFIG. BPI_SYNC_MODE||Disable||Disable, Type1, Type2||
Sets the BPI synchronous configuration mode for different types of BPI flash devices.
Disable (the default) disables the synchronous configuration mode.
Type1 enables the synchronous configuration mode and settings to support the Micron G18(F) family.
Type2 enables the synchronous configuration mode and settings to support the Micron (Numonyx) P30 and P33 families.
|BITSTREAM.CONFIG. CCLKPIN||Pullup||Pullup, Pullnone||Adds an internal pull-up to the Cclk pin. The Pullnone setting disables the pullup.|
|BITSTREAM.CONFIG. PERSIST||No||No, Yes||Prohibit usage of the configuration pins as user I/O and persist after configuration.|
|BITSTREAM.CONFIG. CONFIGRATE||2.7||2.7, 5.3, 8.0, 10.6, 21.3, 31.9, 36.4, 51.0, 56.7, 63.8, 72.9, 85.0, 102.0, 127.5, 170.0||Bitstream generation uses an internal oscillator to generate the configuration clock, Cclk, when configuring is in a master mode. Use this sub-option to select the rate for Cclk.|
|BITSTREAM.CONFIG. D00_MOSI||Pullup||Pullup, Pulldown, Pullnone||Adds an internal pull-up, pull-down, or neither to the D00_MOSI pin. Select Pullnone to disable both the pull-up resistor and the pull-down resistor on the D00_MOSI pin.|
|BITSTREAM.CONFIG. D01_DIN||Pullup||Pullup, Pulldown, Pullnone||Adds an internal pull-up, pull-down, or neither to the D01_DIN pin. Select Pullnone to disable both the pull-up resistor and the pull-down resistor on the D01_DIN pin.|
|BITSTREAM.CONFIG. D02||Pullup||Pullup, Pulldown, Pullnone||Adds an internal pull-up, pull-down, or neither to the D02 pin. Select Pullnone to disable both the pull-up resistor and the pull-down resistor on the D02 pin.|
|BITSTREAM.CONFIG. D03||Pullup||Pullup, Pulldown, Pullnone||Adds an internal pull-up, pull-down, or neither to the D03 pin. Select Pullnone to disable both the pull-up resistor and the pull-down resistor on the D03 pin.|
|BITSTREAM.CONFIG. DCIUPDATEMODE||AsRequired||AsRequired, Quiet, Safe||Controls how often the Digitally Controlled Impedance circuit attempts to update the impedance match for DCI IOSTANDARDs.|
|BITSTREAM.CONFIG. DONEPIN||Pullup||Pullup, Pullnone||Adds an internal pull-up to the DONE pin. The Pullnone setting disables the pullup. Use DonePin only if you intend to connect an external pull-up resistor to this pin. The internal pull-up resistor is automatically connected if you do not use DonePin.|
|BITSTREAM.CONFIG. EXTMASTERCCLK_EN||Disable||Disable, Div-1, Div-2, Div-3. Div-4, Div-6, Div-8, Div-12, Div-16, Div-24, Div-48||Allows an external clock to be used as the configuration clock for all master modes. The external clock must be connected to the dual-purpose EMCCLK pin.|
|BITSTREAM.ENCRYPTION. FAMILY_KEY_FILEPATH||None||Path to familyKey.cfg||
Specifies the install location of the Family Key. No specific directory is required.
Xilinx® does not provide the family key as part of the Xilinx Tool Suite. Customers must send a request for the family key to firstname.lastname@example.org. The family key is then distributed to qualified customers through the Product Licensing site on https://www.xilinx.com.
|BITSTREAM.CONFIG. INITPIN||Pullup||Pullup, Pullnone||Specifies whether you want to add a Pullup resistor to the INIT pin, or leave the INIT pin floating.|
|BITSTREAM.CONFIG. M0PIN||Pullup||Pullup, Pulldown, Pullnone||Adds an internal pull-up, pull-down, or neither to the M0 pin. Select Pullnone to disable both the pull-up resistor and the pull-down resistor on the M0 pin.|
|BITSTREAM. CONFIG.M1PIN||Pullup||Pullup, Pulldown, Pullnone||Adds an internal pull-up, pull-down, or neither to the M1 pin. Select Pullnone to disable both the pull-up resistor and the pull-down resistor on the M1 pin.|
|BITSTREAM.CONFIG. M2PIN||Pullup||Pullup, Pulldown, Pullnone||Adds an internal pull-up, pull-down, or neither to the M2 pin. Select Pullnone to disable both the pull-up resistor and the pull-down resistor on the M2 pin.|
|BITSTREAM.CONFIG. NEXT_CONFIG_ADDR||None||<string>||Sets the starting address for the next configuration in a MultiBoot set up, which is stored in the WBSTAR register.|
|BITSTREAM.CONFIG. NEXT_CONFIG_REBOOT||Enable||Enable, Disable||When set to Disable the IPROG command is removed from the .bit file.|
|BITSTREAM.CONFIG. SELECTMAPABORT||Enable||Enable, Disable||Enables or disables the SelectMAP mode Abort sequence. If disabled, an Abort sequence on the device pins is ignored.|
|BITSTREAM.CONFIG. CONFIGFALLBACK||Enable||Enable, Disable||Enables or disables the loading of a default bitstream when a configuration attempt fails.|
|BITSTREAM.CONFIG. PROGPIN||Pullup||Pullup, Pullnone||Adds an internal pull-up to the PROGRAM_B pin. The Pullnone setting disables the pullup. The pullup affects the pin after configuration.|
|BITSTREAM.CONFIG. PUDC_B||Pullup||Pullup, Pulldown, Pullnone||Adds an internal pull-up, pull-down, or neither to the PUDC_B pin. Select Pullnone to disable both the pull-up resistor and the pull-down resistor on the PUDC_B pin.|
|BITSTREAM.CONFIG. RDWR_B_FCS_B||Pullup||Pullup, Pulldown, Pullnone||Adds an internal pull-up, pull-down, or neither to the RDWR_B_FCS_B pin. Select Pullnone to disable both the pull-up resistor and the pull-down resistor on the RDWR_B_FCS_B pin.|
|BITSTREAM.CONFIG. REVISIONSELECT||00||00, 01, 10, 11||Specifies the internal value of the RS[1:0] settings in the Warm Boot Start Address (WBSTAR) register for the next warm boot.|
|BITSTREAM.CONFIG. REVISIONSELECT_ TRISTATE||Disable||Disable, Enable||
Specifies whether the RS[1:0] 3-state is enabled by setting the option in the Warm Boot Start Address(WBSTAR).
RS[1:0] pins 3-state enable
0: Enable RS 3-state
1: Disable RS 3-state
|BITSTREAM.CONFIG. OVERTEMPSHUTDOWN||Disable||Disable, Enable||Enables the device to shut down when the System Monitor detects a temperature beyond the acceptable operational maximum. An external circuitry set up for the System Monitor is required to use this option.|
|BITSTREAM.CONFIG. SPI_32BIT_ADDR||No||No, Yes||Enables SPI 32-bit address style, which is required for SPI devices with storage of 256 Mb and larger.|
|BITSTREAM.CONFIG. SPI_BUSWIDTH||NONE||NONE, 1, 2, 4, 8||Sets the SPI bus to Dual (x2) or Quad (x4) mode for Master SPI configuration from third party SPI flash devices.|
|BITSTREAM.CONFIG. SPI_FALL_EDGE||No||No, Yes||Sets the FPGA to use a falling edge clock for SPI data capture. This improves timing margins and may allow faster clock rates for configuration.|
|BITSTREAM.CONFIG. TCKPIN||Pullup||Pullup, Pulldown, Pullnone||Adds a pull-up, a pull-down, or neither to the TCK pin, the JTAG test clock. The Pullnone setting shows that there is no connection to either the pull-up or the pull-down.|
|BITSTREAM.CONFIG. TDIPIN||Pullup||Pullup, Pulldown, Pullnone||Adds a pull-up, a pull-down, or neither to the TDI pin, the serial data input to all JTAG instructions and JTAG registers. The Pullnone setting shows that there is no connection to either the pull-up or the pull-down.|
|BITSTREAM.CONFIG. TDOPIN||Pullup||Pullup, Pulldown, Pullnone||Adds a pull-up, a pull-down, or neither to the TDO pin, the serial data output for all JTAG instruction and data registers. The Pullnone setting shows that there is no connection to either the pull-up or the pull-down.|
|BITSTREAM.CONFIG. TIMER_CFG||Enables the Watchdog Timer in Configuration mode and sets the value. This option cannot be used at the same time as TIMER_USR.|
|BITSTREAM.CONFIG. TIMER_USR||Enables the Watchdog Timer in Configuration mode and sets the value. This option cannot be used at the same time as TIMER_CFG.|
|BITSTREAM.CONFIG. TMSPIN||Pullup||Pullup, Pulldown, Pullnone||Adds a pull-up, pull-down, or neither to the TMS pin, the mode input signal to the TAP controller. The TAP controller provides the control logic for JTAG. The Pullnone setting shows that there is no connection to either the pull-up or the pull-down.|
|BITSTREAM.CONFIG. UNUSEDPIN||Pulldown||Pullup, Pulldown, Pullnone||Adds a pull-up, a pull-down, or neither to unused SelectIO pins (IOBs). It has no effect on dedicated configuration pins. The list of dedicated configuration pins varies depending upon the architecture. The Pullnone setting shows that there is no connection to either the pull-up or the pull-down.|
|BITSTREAM.CONFIG. USERID||0xFFFFFFFF||0xFFFFFFFF||Used to identify implementation revisions. You can enter up to an 8-digit hexadecimal string in the User ID register.|
|BITSTREAM.CONFIG. USR_ACCESS||None||None, <8-digit hex string>, TIMESTAMP||Writes an 8-digit hexadecimal string, or a timestamp into the AXSS configuration register. The format of the timestamp value is ddddd MMMM yyyyyy hhhhh mmmmmm ssssss : day, month, year (year 2000 = 00000), hour, minute, seconds. The contents of this register may be directly accessed by the FPGA fabric via the USR_ACCESS primitive.|
|BITSTREAM.CONFIG. INITSIGNALSERROR||Enable||Enable, Disable||When Enabled, the INIT_B pin asserts to '0' when a configuration error is detected.|
|BITSTREAM. ENCRYPTION. ENCRYPT||No||No, Yes||Encrypts the bitstream.|
|BITSTREAM.ENCRYPTION.DEBUGKDFKEYS||No||No, Yes||When enabled, generate a debug file containing all the keys generated in the KDF mode.|
|BITSTREAM. ENCRYPTION. ENCRYPTKEYSELECT||bbram||bbram, efuse||Determines the location of the AES encryption key to be used, either from the battery-backed RAM (BBRAM) or the eFUSE register. This property is only available when the Encrypt option is set to True.|
|BITSTREAM. ENCRYPTION. OBFUSCATEKEY||Disable||Disable, Enable||When the AES key is not read-secured, a read of the key returns the CRC hash of the key instead of the actual key value.|
|BITSTREAM. ENCRYPTION. KEY0||Key0 sets the 64-bit AES encryption key for bitstream encryption. To get the pick setting, leave this blank generator to select a random number for the value. To use this option, you must first set Encrypt to Yes.|
|BITSTREAM. ENCRYPTION. STARTIV0||Sets the starting AES initial vector value. Only the first 96 bits of the 128-bit value are used for the initialization vector. To use this option, you must first set Encrypt to Yes.|
|BITSTREAM. ENCRYPTION. STARTIVOBFUSCATE||Sets the 128-bit starting obfuscate initial vector value. To use this option, you must first set Encrypt to Yes.|
|BITSTREAM.ENCRYPTION.KDFFIXEDINPUT||None||Optional 60-byte fixed input value, specified as a 120-digit hexadecimal value. This 60-byte fixed input along with the 4-Byte counter serves as the 64-Byte fixed input data to the KDF pseudo-random-function (PRF) to generate the 32-byte key output (KO). If not specified, write_bitstream generates a 60-byte pseudo-random fixed input value using RAND_bytes.|
|BITSTREAM.ENCRYPTION.KDFSEED||None||Optional 32-byte seed value for the KDF, specified as a 64-digit hexadecimal value.If not specified, write_bitstream takes the Key0 value from an input .NKY file as the seed value. If not specified and if no Key0 input from an NKY file exists, then write_bitstream generates a 32-byte pseudo-random seed value via RAND_bytes.|
|BITSTREAM. ENCRYPTION. KEYFILE||Specifies the name of the input encryption file (with a .nky file extension). To use this option, you must first set Encrypt to Yes.|
|BITSTREAM. ENCRYPTION. KEYLIFE||32||4 up to 2147483647||The number of 128-bit encryption blocks over which a single key should be used for AES-GCM authenticated bitstreams.|
|BITSTREAM. ENCRYPTION. RSAKEYLIFEFRAMES||8||8 up to 2147483647||Specifies how many configuration frames should be used for any given AES-256 key when RSA Public Key Authentication is specified. A value of 8 configuration frames is equivalent to using the key for 246 encryption blocks.|
|BITSTREAM. GENERAL. COMPRESS||False||True, False||Uses the multiple frame write feature in the bitstream to reduce the size of the bitstream, not just the bit file. Using compress does not guarantee that the size of the bitstream will shrink.|
Controls the generation of a Cyclic Redundancy Check (CRC) value in the bitstream. When enabled, a unique CRC value is calculated based on bitstream contents. If the calculated CRC value does not match the CRC value in the bitstream, the device will fail to configure. When CRC is disabled a constant value is inserted in the bitstream in place of the CRC, and the device does not calculate a CRC.
The CRC default value is Enable, except when BITSTREAM.ENCRYPTION.ENCRYPT is Yes, the CRC is disabled.
|BITSTREAM.GENERAL. DEBUGBITSTREAM||No||No, Yes||Lets you create a debug bitstream. A debug bitstream is significantly larger than a standard bitstream. DebugBitstream can be used only for master and slave serial configurations. DebugBitstream is not valid for Boundary Scan or Slave Parallel/SelectMAP. In addition to a standard bitstream, a debug bitstream offers the following features: Writes 32 0s to the LOUT register after the synchronization word. Loads each frame individually. Performs a Cyclic Redundancy Check (CRC) after each frame. Writes the frame address to the LOUT register after each frame.|
|BITSTREAM.GENERAL. PERFRAMECRC||No||No, Yes||Inserts CRC values at regular intervals within bitstreams. These values validate the integrity of the incoming bitstream and can flag an error (shown on the INIT_B pin and the PRERROR port of the ICAP) prior to loading the configuration data into the device. While most appropriate for partial bitstreams, when set to Yes, this property inserts the CRC values into all bitstreams, including full device bitstreams.|
|BITSTREAM.GENERAL. SYSMONPOWERDOWN||Disable||Disable, Enable||Enables the device to power down SYSMON to save power. Only recommended for permanently powering down SYSMON.|
|BITSTREAM.GENERAL. DISABLE_JTAG||No||No, Yes||Disables communication to the Boundary Scan (BSCAN) block via JTAG after configuration.|
|BITSTREAM.GENERAL. JTAG_SYSMON||Enable||Enable, Disable, StatusOnly||Enables or disables the JTAG connection to SYSMON.|
|BITSTREAM.READBACK. ICAP_SELECT||Auto||Auto, Top, Bottom||Selects between the top and bottom ICAP ports.|
|BITSTREAM.READBACK. ACTIVERECONFIG||No||No, Yes||Prevents the assertions of GHIGH and GSR during configuration. This is required for the active partial reconfiguration enhancement features.|
|BITSTREAM. READBACK. SECURITY||None||None, Level1, Level2||
Specifies whether to disable Readback and Reconfiguration.
Specifying Security Level1 disables Readback.
|BITSTREAM.STARTUP. DONE_CYCLE||4||4, 1, 2, 3, 5, 6||Selects the Startup phase that activates the FPGA Done signal. Done is delayed when DonePipe=Yes.|
|BITSTREAM.STARTUP. GTS_CYCLE||5||5, 1, 2, 3, 4, 6, Done, Keep||Selects the Startup phase that releases the internal 3-state control to the I/O buffers.|
|BITSTREAM.STARTUP. GWE_CYCLE||6||6, 1, 2, 3, 4, 5, Done, Keep||Selects the Startup phase that asserts the internal write enable to flip-flops, LUT RAMs, and shift registers. GWE_cycle also enables the BRAMS. Before the Startup phase, both block RAMs writing and reading are disabled.|
|BITSTREAM.STARTUP. LCK_CYCLE||NoWait||NoWait, 0, 1, 2, 3, 4, 5, 6||Selects the Startup phase to wait until MMCM/PLLs lock. If you select NoWait, the Startup sequence does not wait for MMCM/PLLs to lock.|
|BITSTREAM.STARTUP. MATCH_CYCLE||Auto||Auto, NoWait, 0, 1, 2, 3, 4, 5, 6||
Specifies a stall in the Startup cycle until digitally controlled impedance (DCI) match signals are asserted. DCI matching does not begin on the Match_cycle. The Startup sequence waits in this cycle until DCI has matched. Given that there are a number of variables in determining how long it takes DCI to match, the number of CCLK cycles required to complete the Startup sequence may vary in any given system. Ideally, the configuration solution should continue driving CCLK until DONE goes High.
When the Auto setting is specified,