This bridge type is intended for designs that use Xilinx Virtual Cable (XVC) to remotely debug an FPGA or SoC device through Ethernet or other interfaces without the need for JTAG cable. In this mode, the Debug Bridge expects to receive XVC commands via JTAG interface driven by user logic. For more information see the Debug Bridge LogiCORE IP Product Guide (PG245).
Figure 1. JTAG to BSCAN Debug Bridge