From PCIe to JTAG - 2022.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

Document ID
UG908
Release Date
2022-10-19
Version
2022.2 English

In a PCIe setup, you can use the Debug Bridge in the PCIe to JTAG mode to communicate with the debug cores. In this mode, Debug Bridge connects to the Extended Configuration Interface of the PCIe® IP, which in turn can communicate over JTAG to the debug hub on a different target FPGA.

Figure 1. PCIe® to JTAG Debug Bridge Used with PCIe Extended Configuration Interface