ILA Cross Triggering feature enables cross triggering between ILA cores, and between ILA cores and a processor for example, Zynq®-7000 SoC. This feature is useful for when you want to trigger between two ILA cores that are in different clock domains, or perform hardware/software cross triggering between a processor and an ILA core.
For using cross trigger feature, at core generation time, you should configure the ILA core to have dedicated trigger input ports (TRIG_IN and TRIG_IN_ACK) and dedicated trigger output ports (TRIG_OUT and TRIG_OUT_ACK). If you want to use the ILA trigger input or output signals, you must use the HDL instantiation method of adding ILA cores to your design.
TRIG_OUT_ACK signal is an indication to the ILA core (another ILA, user design, or processor) that TRIG_OUT is properly received and causes the ILA to lower the TRIG_OUT signal on receiving TRIG_OUT_ACK.
In other words, TRIG_OUT will remain HIGH until TRIG_OUT_ACK is available. If TRIG_OUT_ACK signal is tied to LOW then TRIG_OUT remains HIGH until the user re-arms the ILA. Only then the TRIG_OUT goes LOW. You can rearm the ILA if TRIG_OUT_ACK is tied to LOW.
A typical cross trigger setup is illustrated below where ILA2 cross triggers into ILA1. The TRIG_OUT signal of ILA2 is connected to the TRIG_IN signal of ILA1. The TRIG_IN_ACK signal of ILA 1 is connected to the TRIG_OUT_ACK signal of ILA2.
(ILA 2) trig_out -> (ILA 1) trig_in (ILA 1) trig_in_ack -> (ILA 2) trig_out_ack
- It is assumed that the logic driving the
trig_inport is synchronous to the ILA clk.
- It takes 1 clk cycle for the
trig_in_acksignal to get asserted after
- It takes 9 clk cycles for the
trig_outsignal to get asserted when
trig_inis used or trigger condition is met.
trig_out_acksignals go low only when trigger signals are de-asserted.
For a detailed tutorial that covers using the Cross Trigger feature between the FPGA fabric and the Zynq-7000 SoC processor, see the Vivado Design Suite Tutorial: Embedded Processor Hardware Design (UG940).