You can identify signals for debugging at the HDL source level prior to synthesis by using the mark_debug constraint. Nets corresponding to signals marked for debug in HDL are automatically listed in the Debug window under the Unassigned Debug Nets folder.
Note: In the Debug window, the Debug Nets view is a more net-centric view of nets that you have
selected for debug. The Debug Cores view is a more core-centric view where you can view
and set core properties.
The procedure for marking nets for debug depends on whether you are working with an RTL source-based project or a synthesized netlist-based project. For an RTL netlist-based project:
- Using the Vivado synthesis feature you can optionally mark HDL signals for debug using the mark_debug constraint in VHDL and Verilog source files. The valid values for the mark_debug constraint are "TRUE" or “FALSE”. The Vivado synthesis feature does not support the “SOFT” value.
For a synthesized netlist-based project:
- Using the Synopsys® Synplify® synthesis tool, you can optionally mark nets for debug using the mark_debug and syn_keep constraints in VHDL or Verilog, or using the mark_debug constraint alone in the Synopsys Design Constraints (SDC) file. Synplify does not support the “SOFT” value, as this behavior is controlled by the syn_keep attribute.
- Using the Mentor Graphics® Precision® synthesis tool, you can optionally mark nets for debug using the mark_debug constraint in VHDL or Verilog.
The following subsections provide syntactical examples for Vivado synthesis, XST, Synplify, and Precision source files.