Revision History - 2022.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)
Document ID
UG908
Release Date
2022-10-19
Version
2022.2 English

The following table shows the revision history for this document.

Section Revision Summary
10/19/2022 Version 2022.2
Debug Hub Updated IP name.
PDI Verify for Versal ACAP Devices Added new section.
ILA Core and Timing Considerations Added bullets to the list.
Programming FTDI Devices for Vivado Hardware Manager Support Updated the section.
Zynq-7000 Configuration Memory Devices Added a note to the end of the table.
Zynq UltraScale+ MPSoC Configuration Memory Devices Added a note to the end of the table.
Zynq UltraScale+ RFSoC Configuration Memory Devices Added a note to the end of the table.
Versal Configuration Memory Devices Added a row and a note to the end of the table.
4/26/2022 Version 2022.1
Xilinx Virtual Cable (XVC) Updated the content.
Vivado Debug Bridge IP and Xilinx Virtual Cable (XVC) Flow Updated From AXI to BSCAN.
Xilinx Virtual Cable (XVC) Flow for Versal Devices Updated the content.
Device Configuration Bitstream or PDI Settings Updated Artix, Virtex, and Kintex UltraScale+ Bitstream Settings, UltraScale Bitstream Settings
Configuration Memory Support Updated all the tables.