The Vivado® IDE provides a quick and easy way to generate a design that helps you debug and verify your system that uses Xilinx high-speed gigabit transceiver (GT) technology. The in-system serial I/O debugging flow has three distinct phases:
- IBERT Core generation phase: Customizing and generating the IBERT core that best meets your hardware high-speed serial I/O requirements.
- IBERT Example Design Generation and Implementation phase: Generating the example design for the IBERT core generated in the previous step.
- Serial I/O Analysis phase: Interacting with the IBERT IP contained in the design to debug and verify issues in your high-speed serial I/O links.
The rest of this chapter shows how to complete the first two phases. The third phase is covered in Debugging the Serial I/O Design in Hardware.