An alternative way to program FPGAs and configuration memory devices is through the use of a serial vector format (SVF) file. The SVF file generated through Vivado® Design Suite and Vivado Lab Edition contains low level JTAG instructions and data required to program these devices. Once the file is generated it can be used by boundary scan test tools independent of the Vivado IDE.
The general steps to create an SVF file are as follows:
- Create an SVF offline target.
- Open the created SVF target.
- Add devices to the target to define the SVF JTAG scan chain.
- Program FPGAs or configuration memory devices.
- Write SVF.
- Close SVF target.
- (Optional) Execute SVF.
In step 4, the program operations are recorded in sequential order and stored a cached file. The cached file is then written out to a target destination in step 5. After the file is created, it can be used by boundary scan tools or executed through Vivado Design Suite or Vivado Lab Edition tools.