Debugging AXI interfaces often involves triggering on three specific kinds of AXI events: End of the Address Command, End of Data Beat, and Write Response. It is often required to trigger on one or more of these events on different interface channels. For instance, to implement the trigger condition of "End of Read Address Command OR End of Write Address Command", the following equation is required:
However, this requires a "Sum of Products" or "SOP"-style Boolean equation that is not possible to implement when the required AXI signals (such as ARVALID and ARREADY) reside on different probe ports. To facilitate this type of triggering, the required *VALID, *READY, and *LAST control signals are concatenated together onto a single probe port as shown in the following table.
|Description||Probe Name||Bit 2||Bit 1||Bit 0|
|Read Address channel control signals||*ar_ctrl[1:0]||N/A||ARREADY||ARVALID|
|Read Data channel control signals||*r_ctrl[2:0]||RLAST||RREADY||RVALID|
|Write Address channel control signals||*aw_ctrl[1:0]||N/A||AWREADY||AWVALID|
|Write Data channel control signals||*w_ctrl[2:0]||WLAST||WREADY||WVALID|
|Write Response channel control signals||*b_ctrl[1:0]||N/A||BREADY||BVALID|
The following table shows how to use both the individual AXI control signal probes as well as the AXI channel control probes to implement useful basic trigger and capture control equations. The following figure shows how to implement the "End of Read Address Command OR End of Write Address Command" event using the basic trigger setup GUI.
|AXI Event||Individual AXI Control Signals||Combined AXI Channel Control Probe|
|End of the Read Address Command||((ARVALID == 1) && (ARREADY == 1))||(*ar_ctrl == 2'b11)|
|End of the Last Read Data Beat||((RVALID == 1) && (RREADY == 1) && (RLAST == 1))||(*r_ctrl == 3'b111)|
|End of the (Non-Last) Read Data Beat||((RVALID == 1) && (RREADY == 1) && (RLAST == 0))||(*r_ctrl == 3'b011)|
|End of the Write Address Command||((AWVALID == 1) && (AWREADY == 1))||(*aw_ctrl == 2'b11)|
|End of the Write Read Data Beat||((WVALID == 1) && (WREADY == 1) && (WLAST == 1))||(*w_ctrl == 3'b111)|
|End of the (Non-Last) Read Data Beat||((WVALID == 1) && (WREADY == 1) && (WLAST == 0))||(*w_ctrl == 3'b011)|