The next step after marking nets for debugging is to assign them to debug cores. The Vivado Design Suite provides an easy to use Set up Debug wizard to help guide you through the process of automatically creating the debug cores and assigning the debug nets to the inputs of the cores.
To use the Set up Debug wizard to insert the debug cores:
- Optionally, select a set of nets for debugging either using the unassigned nets list or direct net selection.
- Select Set up Debug in the Flow Navigator under the Synthesized Design section. from the Vivado Design Suite main menu, or click
- Click Next to get to the Specify Nets to Debug panel (see the following figure).
- Optionally, click Find Nets to Add to add more nets or remove existing nets from the table. You can also right-click a debug net and select Remove Nets to remove nets from the table.
Important: You can also select nets in the Netlist or other windows, then drag them to the list of Nets to Debug.
- Right-click a debug net and select Select Clock
Domain to change the clock domain to be used to sample value on
the net. Note: The Set up Debug wizard attempts to automatically select the appropriate clock domain for the debug net by searching the path for synchronous elements. Use the Select Clock Domain dialog window to modify this selection as needed, but be aware that each clock domain present in the table results in a separate ILA core instance.Tip: Refer to ILA Core and Timing Considerations in UltraFast Design Methodology Guide for FPGAs and SOCs (UG949) for tips on helping to minimize timing impact of the ILA Core.
- Once you are satisfied with the debug net selection, click Next. Note: The Set up Debug wizard inserts one ILA core per clock domain. The nets that were selected for debug are assigned automatically to the probe ports of the inserted ILA cores. The last wizard screen shows the core creation summary displaying the number of clocks found and ILA cores to be created and/or removed.
- If you want to enable either advanced trigger mode or basic capture mode, use
the corresponding check boxes to do so. Click Next to move to the last panel. Note: The advanced trigger mode and basic capture mode features, when used in the Vivado Hardware Manager, are described in more detail in Debugging Logic Designs in Hardware.
- If you are satisfied with the results, click Finish to insert and connect the ILA cores in your synthesized
- Configure the ILA core general options such as ILA data depth (C_DATA_DEPTH),
number of input pipe stages (C_INPUT_PIPE_STAGES), enabling the capture control
feature (C_EN_STRG_QUAL), and enabling the advanced trigger feature
(C_ADV_TRIGGER). Refer to Modifying Properties on the Debug Cores for
descriptions of these options.
- The debug nets are now assigned to the ILA debug core, as shown in the following