The device configuration settings for Versal ACAP devices are available for use with the
set_property <Setting> <Value> [current_design]Vivado tool Tcl command are shown in the following table.
Note: On the Versal ACAP architecture, most programmable device image settings previously supported as a Bitstream setting are configured in either the Control, Interface, and Processing System (CIPS) IP or as Bootgen settings. See the Control, Interface and Processing System LogiCORE IP Product Guide (PG352) or the Bootgen User Guide (UG1283) for more information.
|Setting||Default Value||Possible Values||Description|
|BITSTREAM.CONFIG.USR_ACCESS||None||None, <8-digit hex string>, TIMESTAMP||Writes an 8-digit hexadecimal string, or a timestamp into the USR_ACCESS register in the PLM_RTCA module. The format of the timestamp value is ddddd MMMM yyyyyy hhhhh mmmmmm ssssss : day, month, year (year 2000 = 00000), hour, minute, seconds. The contents of this register may be directly accessed via the PS or an AXI Manager in the PL.|
|BITSTREAM.GENERAL.COMPRESS||True||True, False||Use the run length encoding algorithm to reduce the size of the PL configuration data. In most cases this can reduce the size of the PL configuration data.|
|BITSTREAM.GENERAL.CRC||False||True, False||Controls the generation of a Cyclic Redundancy Check (CRC) value in the PL portion of the PDI. When enabled, a unique CRC value is calculated based on the PL portion of the PDI contents. If the calculated CRC value does not match the CRC value in the PDI the device will fail to configure.|
|BITSTREAM.GENERAL.PERFRAMECRC||False||True, False||Inserts CRC values at regular intervals in the PL portion of the PDI. These values validate the integrity of the incoming configuration data and can flag an error prior to loading the configuration data into the device. While most appropriate for partial PDI's, when set to Yes this property inserts the CRC values into all PDI's including full device images.|