Logic that is in the static region, and therefore is never partially reconfigured, can still be reconfigured dynamically through the Dynamic Reconfiguration Port (DRP). The DRP can be used to configure logic elements such as MMCMs, PLLs, and serial transceivers (MGTs).
Information about the DRP and dynamic reconfiguration, including how to use the DRP for specific design resources, can be found in these documents:
- 7 Series FPGAs Configuration User Guide (UG470)
- 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)
- 7 Series FPGAs GTP Transceivers User Guide (UG482)
- MMCM and PLL Dynamic Reconfiguration Application Note (XAPP888)
- UltraScale Architecture Configuration User Guide (UG570)
- UltraScale Architecture Clocking Resources User Guide (UG572)
- UltraScale Architecture GTH Transceivers User Guide (UG576)
- UltraScale Architecture GTY Transceivers User Guide (UG578)