Dynamic Function eXchange (DFX) in Xilinx® FPGAs, SoCs, and ACAPs introduces new design requirements compared to traditional solutions. These requirements include unique approaches to source and run management, as both bottom-up synthesis and multi-pass implementation are needed. Before 2021, only non-project Tcl-based and RTL project-based solutions have been available in Vivado® . Vivado 2021.1 introduced an IP-centric project-based environment, which includes new capabilities for block designs and other aspects of IP integrator.
This tutorial is intended to summarize the Vivado tool flow, from project creation to partial image creation for Versal® ACAP targets using the Block Design Container feature in IP integrator. This fundamental flow can be used to apply to Virtex and Kintex® UltraScale™ and UltraScale+™ targets as well. The previous lab covers the equivalent solution for Zynq® UltraScale+ targets.