DFX BDC Project Flow in IP Integrator for Zynq UltraScale+ - 2022.2 English

Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947)

Document ID
UG947
Version
2022.2 English

Dynamic Function eXchange (DFX) in Xilinx® FPGAs, SoCs, and ACAPs introduces new design requirements compared to traditional solutions. These requirements include unique approaches to source and run management, as both bottom-up synthesis and multi-pass implementation are needed. Before 2021, only non-project Tcl-based and RTL project-based solutions have been available in Vivado® . Vivado® 2021.2 introduced an IP-centric project-based environment, which includes new capabilities for block designs and other aspects of IP integrator.

This tutorial is intended to summarize the Vivado tool flow, from project creation to partial bitstream creation for Zynq® UltraScale+™ MPSoC and RFSoC targets using the Block Design Container feature in IP integrator. This fundamental flow can be used to apply to Virtex and Kintex® UltraScale™ and UltraScale+™ targets as well. The next lab covers the equivalent solution for Versal® ACAP targets.