The capabilities of debug within DFX designs in Versal continue from the flow supported in UltraScale+. Once instantiated, debug cores can be automatically connected to the HSDP in Versal like was done for BSCAN, as long as the ports on the Reconfigurable Partition boundary has been defined. In UltraScale+ this was done with a set of 12 explicitly named S_BSCAN ports (or tagged with properties), whereas in Versal, connection to the HSDP is accomplished via NoC.