ISERDESE3 - 2022.2 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2022-10-19
Version
2022.2 English

Primitive: Input SERial/DESerializer

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: SERDES
  • Families: UltraScale, UltraScale+

Introduction

In component mode, the ISERDESE3 in UltraScale devices is a dedicated serial-to-parallel converter with specific clocking and logic features designed to facilitate the implementation of high-speed source-synchronous applications. The ISERDESE3 avoids the additional timing complexities encountered when designing deserializers in the device fabric. ISERDESE3 features include: Dedicated Deserializer/Serial-to-Parallel Converter, which enables high-speed data transfer without requiring the device fabric to match the input data frequency. This converter supports both single data rate (SDR) and double data rate (DDR) modes. In SDR mode, the serial-to-parallel converter creates a 4- bit wide parallel word by retrieving data from every other Q pin. In DDR mode, the serial-to-parallel converter creates an 8-bit-wide parallel word.

Port Descriptions

Port Direction Width Function
CLK Input 1 The high-speed clock input (CLK) is used to clock in the input serial data stream.
CLK_B Input 1 The inverted high-speed clock input.
CLKDIV Input 1 The divided clock input (CLKDIV) is typically a divided version of CLK (depending on the width of the implemented deserialization). It drives the output of the serial-to-parallel converter and the CE module.
D Input 1 The serial input data port (D) is the serial (high-speed) data input port of the ISERDESE3. This port accepts data from the IOB or device Fabric.
FIFO_EMPTY Output 1 FIFO empty flag.
FIFO_RD_CLK Input 1 FIFO read clock.
FIFO_RD_EN Input 1 Enables reading the FIFO when asserted.
INTERNAL_DIVCLK Output 1 Internally divided down clock used to launch data from ISERDES to fabric when FIFO is disabled (do not connect).
Q<7:0> Output 8 8-bit registered output
RST Input 1 Asynchronous Reset, active level based on IS_RST_INVERTED.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog Yes

Available Attributes

Attribute Type Allowed Values Default Description
DATA_WIDTH DECIMAL 8, 4 8 Defines the width of the serial-to-parallel converter. Running in SDR mode is done by retrieving data from every other Q pin.
FIFO_ENABLE STRING "FALSE", "TRUE" "FALSE" Setting FIFO_ENABLE to TRUE uses the FIFO and setting FIFO_ENABLE to FALSE bypasses the FIFO.
FIFO_SYNC_MODE STRING "FALSE", "TRUE" "FALSE" Set to FALSE when the ISERDES internal FIFO write clock and the FIFO read clock accessed from the FPGA logic are from separate or common clock domains. This is the preferred selection because it supports all clocking options. TRUE is reserved for later use.
IDDR_MODE STRING "FALSE", "TRUE" "FALSE" Internal property for Vivado primitive mapping. Do not modify.
IS_CLK_B_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether the CLK_B pin is active-Low or active-High.
IS_CLK_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether the CLK pin is active-High or active-Low.
IS_RST_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether the RST pin is active-High or active-Low.
SIM_DEVICE STRING "7SERIES", "ULTRASCALE" "ULTRASCALE" Set the device version for simulation functionality.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- ISERDESE3: Input SERial/DESerializer
--            UltraScale
-- Xilinx HDL Language Template, version 2022.2

ISERDESE3_inst : ISERDESE3
generic map (
   DATA_WIDTH => 8,                 -- Parallel data width (4,8)
   FIFO_ENABLE => "FALSE",          -- Enables the use of the FIFO
   FIFO_SYNC_MODE => "FALSE",       -- Always set to FALSE. TRUE is reserved for later use.
   IS_CLK_B_INVERTED => '0',        -- Optional inversion for CLK_B
   IS_CLK_INVERTED => '0',          -- Optional inversion for CLK
   IS_RST_INVERTED => '0',          -- Optional inversion for RST
   SIM_DEVICE => "ULTRASCALE_PLUS"  -- Set the device version for simulation functionality (ULTRASCALE,
                                    -- ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
)
port map (
   FIFO_EMPTY => FIFO_EMPTY,           -- 1-bit output: FIFO empty flag
   INTERNAL_DIVCLK => INTERNAL_DIVCLK, -- 1-bit output: Internally divided down clock used when FIFO is
                                       -- disabled (do not connect)

   Q => Q,                             -- 8-bit registered output
   CLK => CLK,                         -- 1-bit input: High-speed clock
   CLKDIV => CLKDIV,                   -- 1-bit input: Divided Clock
   CLK_B => CLK_B,                     -- 1-bit input: Inversion of High-speed clock CLK
   D => D,                             -- 1-bit input: Serial Data Input
   FIFO_RD_CLK => FIFO_RD_CLK,         -- 1-bit input: FIFO read clock
   FIFO_RD_EN => FIFO_RD_EN,           -- 1-bit input: Enables reading the FIFO when asserted
   RST => RST                          -- 1-bit input: Asynchronous Reset
);

-- End of ISERDESE3_inst instantiation

Verilog Instantiation Template


// ISERDESE3: Input SERial/DESerializer
//            UltraScale
// Xilinx HDL Language Template, version 2022.2

ISERDESE3 #(
   .DATA_WIDTH(8),                 // Parallel data width (4,8)
   .FIFO_ENABLE("FALSE"),          // Enables the use of the FIFO
   .FIFO_SYNC_MODE("FALSE"),       // Always set to FALSE. TRUE is reserved for later use.
   .IS_CLK_B_INVERTED(1'b0),       // Optional inversion for CLK_B
   .IS_CLK_INVERTED(1'b0),         // Optional inversion for CLK
   .IS_RST_INVERTED(1'b0),         // Optional inversion for RST
   .SIM_DEVICE("ULTRASCALE_PLUS")  // Set the device version for simulation functionality (ULTRASCALE,
                                   // ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
)
ISERDESE3_inst (
   .FIFO_EMPTY(FIFO_EMPTY),           // 1-bit output: FIFO empty flag
   .INTERNAL_DIVCLK(INTERNAL_DIVCLK), // 1-bit output: Internally divided down clock used when FIFO is
                                      // disabled (do not connect)

   .Q(Q),                             // 8-bit registered output
   .CLK(CLK),                         // 1-bit input: High-speed clock
   .CLKDIV(CLKDIV),                   // 1-bit input: Divided Clock
   .CLK_B(CLK_B),                     // 1-bit input: Inversion of High-speed clock CLK
   .D(D),                             // 1-bit input: Serial Data Input
   .FIFO_RD_CLK(FIFO_RD_CLK),         // 1-bit input: FIFO read clock
   .FIFO_RD_EN(FIFO_RD_EN),           // 1-bit input: Enables reading the FIFO when asserted
   .RST(RST)                          // 1-bit input: Asynchronous Reset
);

// End of ISERDESE3_inst instantiation

Related Information

  • See the UltraScale Architecture SelectIO Resources User Guide (UG571).