OBUFDS_GTE3_ADV - 2022.2 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2022-10-19
Version
2022.2 English

Primitive: Gigabit Transceiver Buffer

  • PRIMITIVE_GROUP: ADVANCED
  • PRIMITIVE_SUBGROUP: GT
  • Families: UltraScale

Introduction

OBUFDS_GTE3_ADV is the gigabit transceiver output pad buffer component in UltraScale devices. The REFCLK signal should be routed to the dedicated reference clock output pins on the serial transceiver, and the user design should instantiate the OBUFDS_GTE3 primitive in the user design. See the Transceivers User Guide for more information on PCB layout requirements, including reference clock requirements.

Port Descriptions

Port Direction Width Function
CEB Input 1 Refer to Transceiver User Guide.
I<3:0> Input 4 Refer to Transceiver User Guide.
O Output 1 Refer to Transceiver User Guide.
OB Output 1 Refer to Transceiver User Guide.
RXRECCLK_SEL<1:0> Input 2 Refer to Transceiver User Guide.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog Recommended

Available Attributes

Attribute Type Allowed Values Default Description
REFCLK_EN_TX_PATH BINARY 1'b0 to 1'b1 1'b1 Refer to Transceiver User Guide.
REFCLK_ICNTL_TX BINARY 5'b00000 to 5'b11111 5'b00000 Refer to Transceiver User Guide.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- OBUFDS_GTE3_ADV: Gigabit Transceiver Buffer
--                  UltraScale
-- Xilinx HDL Language Template, version 2022.2

OBUFDS_GTE3_ADV_inst : OBUFDS_GTE3_ADV
generic map (
   REFCLK_EN_TX_PATH => '1',   -- Refer to Transceiver User Guide.
   REFCLK_ICNTL_TX => "00000"  -- Refer to Transceiver User Guide.
)
port map (
   O => O,                       -- 1-bit output: Refer to Transceiver User Guide.
   OB => OB,                     -- 1-bit output: Refer to Transceiver User Guide.
   CEB => CEB,                   -- 1-bit input: Refer to Transceiver User Guide.
   I => I,                       -- 4-bit input: Refer to Transceiver User Guide.
   RXRECCLK_SEL => RXRECCLK_SEL  -- 2-bit input: Refer to Transceiver User Guide.
);

-- End of OBUFDS_GTE3_ADV_inst instantiation

Verilog Instantiation Template


// OBUFDS_GTE3_ADV: Gigabit Transceiver Buffer
//                  UltraScale
// Xilinx HDL Language Template, version 2022.2

OBUFDS_GTE3_ADV #(
   .REFCLK_EN_TX_PATH(1'b1),   // Refer to Transceiver User Guide.
   .REFCLK_ICNTL_TX(5'b00000)  // Refer to Transceiver User Guide.
)
OBUFDS_GTE3_ADV_inst (
   .O(O),                       // 1-bit output: Refer to Transceiver User Guide.
   .OB(OB),                     // 1-bit output: Refer to Transceiver User Guide.
   .CEB(CEB),                   // 1-bit input: Refer to Transceiver User Guide.
   .I(I),                       // 4-bit input: Refer to Transceiver User Guide.
   .RXRECCLK_SEL(RXRECCLK_SEL)  // 2-bit input: Refer to Transceiver User Guide.
);

// End of OBUFDS_GTE3_ADV_inst instantiation

Related Information

  • See the UltraScale Architecture GTH Transceivers User Guide (UG576)
  • See the UltraScale Architecture GTY Transceivers Advance Specification User Guide (UG578).