PULLUP - 2022.2 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2022-10-19
Version
2022.2 English

Primitive: I/O Pullup

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: WEAK_DRIVER
  • Families: UltraScale, UltraScale+

Introduction

The design element is a weak pullup element that pulls an undriven I/O to a logic one state. For example, if the I/O is 3-stated and not driven by any other element, a logic 1 will exist on the I/O.

Port Descriptions

Port Direction Width Function
O Output 1 Pullup output. Connect directly to a top-level port in the design.

Design Entry Method

Instantiation Yes
Inference Yes, via property
IP and IP Integrator Catalog No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- PULLUP: I/O Pullup
--         UltraScale
-- Xilinx HDL Language Template, version 2022.2

PULLUP_inst : PULLUP
port map (
   O => O  -- 1-bit output: Pullup output (connect directly to top-level port)
);

-- End of PULLUP_inst instantiation

Verilog Instantiation Template


// PULLUP: I/O Pullup
//         UltraScale
// Xilinx HDL Language Template, version 2022.2

PULLUP PULLUP_inst (
   .O(O)  // 1-bit output: Pullup output (connect directly to top-level port)
);

// End of PULLUP_inst instantiation

Related Information

  • See the UltraScale Architecture SelectIO Resources User Guide (UG571).