Limitations of the Module Reference Feature - 2022.2 English

The following limitations exist in the Module Reference feature:

• Because a module reference is not an IP, you cannot specify the Vendor, Library, Name, and Version (VLNV).
• VHDL and Verilog are the only supported languages for module definition. A block design containing a module reference cannot be packaged as an IP. Instead, package the module as an IP separately, and then package the BD including that IP.
• Module Reference blocks cannot be opted out of upgrade while migrating a design from a previous version of Vivado.
• A ModuleRef must not contain CIPS or NOC IP.
• A ModuleRef cannot instantiate one or more DCP modules.
• A ModuleRef cannot instantiate one or more ModuleRefs (Nested ModuleRefs).
• A ModuleRef cannot instantiate a BD using block design container (BDC) technology.
• BD/ XCI will be synthesized in OOC inside module referenced RTL.
  Tip: SystemVerilog and VHDL 2008 are not supported for the module or entity definition at the top-level of the RTL module.
• When you have multiple instances of a module reference on a BD canvas, the module names in the RTL hierarchy must be unique. The user must uniquify all the modules name to ensure that there are no conflicts. Alternatively, a BDC can be used. If the module reference is in the BDC and the BDC is instantiated multiple times, the BDC takes care of uniquifying the module names.