AI Engine IP - 2023.1 English

Versal Adaptive SoC Design Guide (UG1273)

Document ID
UG1273
Release Date
2023-05-16
Version
2023.1 English

To generate an extensible platform for the Vitis environment, the AI Engine IP must be instantiated and connected to the rest of the design. A base platform hardware design includes a block design that contains a minimally configured AI Engine IP block with any memory-mapped slave AXI connections enabled and connected to the dedicated NoC bus masters.

All other configuration of the AI Engine is performed through compilation of the user ADF graph and AI Engine kernels through the Vitis aiecompiler and through Vitis v++ linking of the aiecompiler libadf.a with the extensible platform design. Connections from the AI Engine to the base platform include AXI4-Stream master and slave connections, memory-mapped AXI bus connections to NoC, and clocks for the bus interfaces. AI Engine events triggered within the IP are transferred to memory and via XSDB through the AXI4 connections.

For more information, see the AI Engine LogiCORE IP Product Guide (PG358) and AI Engine Tools and Flows User Guide (UG1076).