Block RAM Primitives - 2023.1 English

Versal Adaptive SoC Design Guide (UG1273)

Document ID
UG1273
Release Date
2023-05-16
Version
2023.1 English

Following are the block RAM primitives in Versal adaptive SoC.

Primitives Supported Aspect Ratios Supported Mode
RAMB36E5

1Kx36

2Kx18

4Kx9

x72 mode when running in simple dual-port (SDP) mode
RAMB18E5

1Kx18

2Kx9

x36 mode when running in SDP mode

In SDP mode, one address reads the RAM and the other address writes to the RAM. You can use different clocks for the read and the write, but the address lines must be separate. The following figures show examples.

Figure 1. Verilog Coding Style for a 512x72 Block RAM in SDP Mode
Figure 2. VHDL Coding Style for a 512x72 Block RAM in SDP Mode

Resets

Following are the types of resets on the block RAM:

  • Synchronous reset on the block RAM output, which uses the RESETRAMA or RESETRAMB pin
  • Asynchronous reset on the block RAM output, which uses the ARST_A or ARST_B pin
    Note: If the ARST_A or ARST_B pin is used, the RESETRAMA, RESETRAMB, RSTREGA, and RSTREGB pins are ignored.
  • Synchronous reset that controls the optional output registers of the block RAM, which uses the RSTREGA or RSTREGB pin

When using asynchronous resets:

  • Both the RAM and optional output register must use the same asynchronous reset.
    Note: If the optional output register does not use the same reset, it is not inferred into the block RAM.
  • The output enables and SRVAL properties are ignored.
  • The asynchronous reset can only reset to a 0 value.

Write Modes

The Versal adaptive SoC block RAMs support the same write modes as AMD UltraScaleā„¢ devices and use the same RTL coding styles:

  • WRITE_FIRST outputs the newly written data onto the output bus.
  • READ_FIRST outputs the previously stored data onto the output bus.
  • NO_CHANGE maintains the previous value of the output bus.

Byte Write Enables

The control ports for byte write enables are the WEA and WEB pins, which vary based on usage:

  • RAMB36E5
    • In non-SDP mode, the WEA and WEB [3:0] pins control 4 bytes of either size 8 or 9.
    • In SDP mode, the WEA and WEB [7:0] pins control 8 bytes of size 8 or 9.
  • RAMB18E5
    • In non-SDP mode, the WEA and WEB [1:0] pins control 2 bytes of size 8 or 9.
    • In SDP mode, pins WEA and WEB [3:0] pins control 4 bytes of 8 or 9.
Note: Size 9 names 8 bits with 1 parity bit.

Currently, Vivado synthesis only infers byte write RAM if sizes of 8 or 9 are used. In addition, Vivado synthesis only infers byte write enable RAM if the enables use one-hot state encoding. For example, in a byte write enabled RAM that is configured as true dual port with a data width of 36, there are 4 different bytes, but only 1 byte can be written to at a time. To infer the block RAM, make sure the RTL adheres to these restrictions.

Asymmetric RAMs

For asymmetric block RAMs in Versal adaptive SoCs, use the same coding styles and rules that you use for asymmetric block RAMs in UltraScale devices. For information on setting up asymmetric block RAMs, see the Vivado Design Suite User Guide: Synthesis (UG901).

Note: Currently, Vivado synthesis does not support asynchronous reset on asymmetric block RAMs in Versal adaptive SoCs.

Using XPMs

Block RAMs can also be inferred using XPMs. The advantage of using this approach is that XPMs always have the correct coding style for any type of RAM needed. For more information on XPMs, see the Vivado Design Suite User Guide: System-Level Design Entry (UG895).