CLBs in Versal adaptive SoC have been enhanced from previous architectures. CLB resources that are no longer supported in Versal adaptive SoC (e.g., CARRY8, MUXF7, MUXF8, MUXF9, etc.) are automatically migrated by inferring the appropriate Versal adaptive SoC block. RTL instantiations are also automatically migrated. For optimal area and timing results, AMD recommends that you do not instantiate CLB UNISIMs that are no longer supported in Versal adaptive SoC and that you re-synthesize your RTL to infer the appropriate Versal adaptive SoC block. For detailed architectural differences, see the Versal Adaptive SoC Configurable Logic Block Architecture Manual (AM005).