CLB Primitives - 2023.1 English

Versal Adaptive SoC Design Guide (UG1273)

Document ID
UG1273
Release Date
2023-05-16
Version
2023.1 English

The configurable logic blocks (CLBs) in Versal adaptive SoCs differ from those in UltraScale devices. Vivado synthesis handles the architectural differences, but you must be aware of the differences noted in the following sections.

Carry Chains

Instead of the CARRY8 primitive in UltraScale devices, Versal adaptive SoCs include a LOOKAHEAD8 primitive. The LOOKAHEAD8 primitive does not include MUXCYs and XORCYs for arithmetic operations. Instead, these operators must be inferred and as a result, the LUT count is slightly higher.

Figure 1. Extra LUTs Before the CARRY Chain

MUXFx Primitives

Versal adaptive SoCs do not include MUXFx primitives. Because MUXFx primitives are often used for address decoding in distributed RAMs, large comparators, or MUX chains, expect extra LUT counts when using these types of structures in Versal adaptive SoCs, as shown in the following figure.

Figure 2. Extra LUTs for Address Decoding