Design Address Map - 2023.1 English

Versal Adaptive SoC Design Guide (UG1273)

Document ID
UG1273
Release Date
2023-05-16
Version
2023.1 English

The Versal adaptive SoC uses a single, unified system address map. All memory-mapped AXI transactions must adhere to this map. The Versal adaptive SoC system address map defines the default address locations of slaves in the Versal adaptive SoC. The address map is built into the PL-based SmartConnect and the NoC. The Vivado IP integrator automatically resolves the base name, offset address, and range of the address region based on the DDR4 memory options selected in the AXI NoC IP customization. These addresses are used by the AXI master to communicate with the DDR. You use the Vivado IP integrator Address Editor to select or automatically assign compliant addresses for all the memory-mapped blocks within the design. For configuration details on the NoC and related IP as well as details on the system address map, see the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).