Power and Error Handling - 2023.1 English

Versal Adaptive SoC Design Guide (UG1273)

Document ID
UG1273
Release Date
2023-05-16
Version
2023.1 English

Zynq UltraScale+ MPSoCs have some power modes that can be mapped to the power modes in Versal adaptive SoC. Peripherals that are power islands are shared in the Versal adaptive SoC. When not in use, these power islands are automatically turned off by the PLM. Many main external power rails that supply power domains are currently supported for sleep states. Additional support will be added in future releases. In Zynq UltraScale+ MPSoCs and Versal adaptive SoCs, PL power management methodology is similar and offers the largest power benefit. For more information, see this link in the Versal Adaptive SoC Board System Design Methodology Guide (UG1506). In Versal adaptive SoC, errors from the DDR, PL, SYSMON, and other system blocks are routed to the PMC error aggregation module (EAM), and the PS errors are routed to the EAM in the PS management controller (PSM). Possible error actions are power-on reset (POR), system reset (SRST), error out, or interrupt software agents.

For detailed architectural differences, see the Versal Adaptive SoC Technical Reference Manual (AM011) and Versal Adaptive SoC System Software Developers Guide (UG1304).