Simulation - 2023.1 English

Versal Adaptive SoC Design Guide (UG1273)

Document ID
UG1273
Release Date
2023-05-16
Version
2023.1 English

The simulation-based method for verifying the adaptable subsystem is referred to as the Vitis hardware emulation flow. Hardware emulation provides detailed visibility into all the elements of the co-simulated system (AI Engine, PS, and PL). You can set breakpoints in the source, trace variables, and plot waveforms for any signal in the PL region of the system, making hardware emulation a useful debug platform to track down the root cause of any potential integration issues.

During hardware emulation, the following tools are used to simulate each element, allowing gradual assembly and verification of the subsystem:

  • AI Engine simulator (aiesimulator) for the AI Engine graph
  • Vivado simulator or a supported third-party simulator for the RTL behavioral models of the PL
  • AMD Quick Emulator (QEMU) for the software code executing on the PS
  • Python, C/C++, or HDL traffic generators can also be used to model data coming from external I/Os or to replace missing functionality with stubs

Meeting performance in hardware emulation is required, but it is not a guarantee of results. Hardware emulation is cycle approximate and therefore, performance results are not final at this stage.

For more information on how to assemble and simulate the adaptable subsystem, see the System Simulation section of the Versal Adaptive SoC Design Process Documentation: System Integration and Validation.