To address the different needs in simulation scope, abstraction, and purpose, AMD provides dedicated flows for the various components of an AMD Versal™ device design, including the AI Engine, PS, and PL. In addition, AMD also provides the ability to co-simulate a complete system comprised of PL, PS and optionally AI Engine components. Individual design teams must validate functionality at the function level prior to integrating in a subset of the system application or the complete system.
The following table shows the simulation models available for each Versal device block.
|PS||QEMU (functional only)||QEMU (functional only)
CIPS Verification IP (VIP)
|NoC||Behavioral SystemVerilog (cycle approximate)||SystemC|
|HBM controller||Behavioral SystemVerilog||Behavioral SystemVerilog|
|PL-based soft memory controller||Behavioral SystemVerilog||Behavioral SystemVerilog|
|CPM||Behavioral SecureIP||Behavioral SecureIP|
|GT||Behavioral SecureIP||File I/O (for Vitis software platform users only)|
|GT-based IP||Behavioral SecureIP||AXI verification IP
File I/O (for Vitis software platform users only)
|Other IP||Varies by IP||Varies by IP|
|AI Engine||SystemC (cycle approximate)||SystemC|
The following sections provide details on the scope and purpose of each of the simulation flows.