System Debug - 2023.1 English

Versal Adaptive SoC Design Guide (UG1273)

Document ID
UG1273
Release Date
2023-05-16
Version
2023.1 English

Debugging designs in PL fabric is similar to previous architectures, but there are several key differences:

  • All fabric debug IP cores have AXI4-Stream slave control interfaces. Previous architectures used a proprietary interface standard.
  • The AXI-Debug Hub IP core has both AXI4-Stream control interfaces (for connection to fabric debug IP cores) and an AXI4-Memory Map slave interface for connection from the host. The Debug Hub IP used in previous architectures relied on proprietary interfaces for connection to the debug cores and host.
  • The debug flows in the Vivado tools now support both automated and manual connectivity between debug hub and debug cores.
  • The JTAG-to-AXI soft debug IP is no longer offered as an option in the Versal adaptive SoC architecture. The DAP and DPC can be used to access AXI-based blocks in your design.
  • The AXI4-Stream-based integrated logic analyzer (ILA) core supports both ILA and System ILA functionality. In previous architectures, these were offered as separate IP cores.
  • The AXI4-Stream-based ILA core supports selection of block RAM or UltraRAM as the trace storage memory.
  • PJTAG is no longer offered as an option in the Versal adaptive SoC architecture. Instead, a single JTAG interface must be used to access DAP and TAP. Check with your debugger vendor to ensure that this solution is supported.

When migrating, consider the following:

Vivado IP integrator
You must manually remove or replace previously instantiated legacy debug cores. Replace the legacy debug cores with the new AXIS-ILA cores in the block design using IP integrator.
Netlist
Xilinx design constraints (XDC) commands for inserting ILA cores into the synthesized design automatically migrate to the new AXIS-ILA debug IP.
RTL
Due to the new interface requirements, the fabric debug cores from previous architectures are not automatically migrated to the new AXI4-Stream-based debug IP cores. If debug cores from previous architectures are instantiated in the design, new debug IP must be manually recustomized, regenerated, and reinstantiated in the design.
IBERT and soft memory controller calibration
The integrated bit error ratio test (IBERT) IP functionality is part of the GT blocks and can be used with any design that uses the transceivers. Memory controller calibration debug is available for both DDRMC blocks and for fabric-based soft memory controller IP.
Debug Hub
Due to the new interface requirements, the legacy Debug Hub is automatically inserted into the netlist only if pl0_resetn is enabled on the CIPS. Alternatively, an AXI4 Debug Hub can be manually added. For details, see this link in the Vivado Design Suite User Guide: Programming and Debugging (UG908).