The AMD Versal™ adaptive SoC is a heterogeneous compute platform with multiple compute engines. A wide range of applications can be mapped on a Versal adaptive SoC, including signal processing for wireless systems, machine learning inference, and video processing algorithms. In addition to multiple compute engines, Versal adaptive SoC offers very high system bandwidth using high-speed serial I/Os, network on chip (NoC), DDR4/LPDDR4 memory controllers, HBM controllers, and multi-rate Ethernet Media Access Controllers (MRMACs). Versal devices are categorized into the Versal Prime, Premium, HBM, AI Core, and AI Edge series. The following figure shows the different system design types and design flows supported for each Versal device series.
The following table shows the system design types and design flows supported for each Versal device series. As shown in the table, a majority of the design flows are based on building a platform.
|Design Type||Device Series||Design Flow||Platform Source||GitHub Examples|
Versal Premium Series
Versal HBM Series
|Traditional||N/A||Versal Device Architecture Tutorials|
Versal Premium Series
Versal HBM Series
|Traditional||N/A||Versal ACAP Embedded Design Tutorial|
|Platform-based||Custom||Versal Prime Series VMK180 Targeted Reference Designs|
|Embedded AI Engine system||
AI Core Series
Versal AI Edge Series
Versal Premium VP2502 and VP2802 devices
|Platform-based||Custom||AI Engine Development Design Tutorials|
Following is a summary of each system design type:
- Hardware-only system
- Programmable logic designs. Create this system using the traditional design flow.
- Embedded system
- Embedded processing system with software running on the Arm® Cortex®-A72 or Cortex-R5F processors and hardware content in the PL. Create this system using either the traditional or platform-based design flow.
- Embedded AI Engine system
- Embedded processing system with software running on the Arm Cortex-A72 or Cortex-R5F processors, hardware content in the PL, and algorithmic content in the AI Engine. Create this system using the platform-based design flow.
Following are the design flows for Versal adaptive SoC:
- Traditional design flow
- In the traditional design flow, the entire PL portion of the system is defined in a single AMD Vivado™ project. This project must include the foundational Versal hardware IP blocks (e.g., Control, Interface, and Processing System (CIPS), NoC, I/O controllers) and any other custom RTL and IP blocks needed for the project. Design sources are added to the Vivado tools and compiled through the Vivado implementation flow. If the system consists of PL components only, the Vivado tools are used to generate a programmable device image (PDI) to program the Versal device. If the system also includes embedded software content, the software application is developed in the AMD Vitis™ environment on top of the fixed hardware design exported from the Vivado tools. This flow is similar to the one traditionally used for AMD Zynq™ UltraScale+™ MPSoCs.
- Platform-based design flow
- In the platform-based design flow, the hardware system is divided into distinct
elements: a reusable base platform developed in Vivado and extensions to the base hardware developed in Vitis through a well-defined set of connectivity
interfaces within an extensible region of the base platform. Most of the
hardware design is developed in Vivado, but
portions of the design best specified in C++ as opposed to a hardware
description language (HDL) are most naturally developed and integrated in
Vitis. Examples of the latter include
AI Engine graphs and kernels, as well as
kernel functions targeting PL compiled through high-level synthesis (HLS).
You choose how to partition your design between base platform and extensible region based on where you will be most productive. Over the course of a design cycle the base hardware and extensible regions can both evolve, and a well-designed base platform can form the basis for multiple applications in which Vitis tools extend the extensible region. Design content can be exported from Vivado to Vitis and vice versa with coupling as loose or as tight as makes sense for the respective development teams, which promotes concurrent development and integration of the different elements comprising a heterogeneous system.