The Vivado IP integrator enables the creation of Block Designs (.bd), or IP subsystems with multiple IP stitched together using the AXI4 interconnect protocol. The IP integrator lets you quickly connect IP cores to create domain specific subsystems and designs, including embedded processor-based designs using AMD Zynq™ UltraScale+™ MPSoC, AMD Zynq™ 7000 SoC, and MicroBlaze™ processors. It can instantiate High-Level Synthesis modules from Vivado HLS, DSP modules from System Generator, and custom user-defined IP as described in Packaging Custom IP and IP Subsystems.
Using Vivado IP integrator you can drag and drop IP onto the design canvas, connect AXI interfaces with one wire, and place ports and interface ports to connect the IP subsystem to the top-level design. These IP block designs can also be packaged as sources (.bd) and reused in other designs. For more information, see the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) or MicroBlaze Processor Embedded Design User Guide (UG1579).