The Vivado simulator, integrated with the Vivado IDE, allows you to simulate the design, and view signals in the waveform viewer, and examine and debug the design as needed. The Vivado simulator is a fully integrated mixed-mode simulator with analog waveform display capabilities. Using the Vivado simulator, you can perform behavioral and structural simulation of designs and full timing simulation of implemented designs.
You can also use third-party simulators to write the Verilog, VHDL netlists, and SDF format files from the open design. You can launch the Mentor Graphics ModelSim and Questa simulators from the Vivado IDE. For more information, see this link in the Vivado Design Suite User Guide: Logic Simulation (UG900).