IP Associated Rules - 2023.1 English

Vivado Design Suite User Guide: System-Level Design Entry (UG895)

Document ID
UG895
Release Date
2023-05-16
Version
2023.1 English

The <ip_associated_rules> tag is used to define a preferred board interface, or a prioritized list of board interfaces that can be assigned to the IP interfaces on a specific IP. This tag is new in the 2.1 schema version of the Board file.

The Designer Assistance feature of the Vivado IP integrator lists the available board interfaces for a given IP interface. See the following link in the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) for more information on Designer Assistance. The <ip_associated_rules> lets you define which board interfaces can be applied to a specific IP interface.

Tip: The <ip_associated_rules> tag can be used to define any IP interface, but is most useful for clocks and resets which typically have more defined board interfaces.
<ip_associated_rules>
  <ip_associated_rule name="default">
    <ip vendor="xilinx.com" library="ip" name="axi_ethernet" version="*" 
ip_interface="mgt_clk">
      <associated_board_interfaces>
  <associated_board_interface name="sgmii_mgt_clk" order="1"/> 
  <associated_board_interface name="sma_mgt_clk" order="0"/> 
      </associated_board_interfaces>
    </ip>
    <ip vendor="xilinx.com" library="ip" name="axi_ethernet" version="*" 
ip_interface="phy_rst_n">
      <associated_board_interfaces>
  <associated_board_interface name="phy_reset_out" order="0"/> 
      </associated_board_interfaces>
    </ip>
    <ip vendor="xilinx.com" library="ip" name="gig_ethernet_pcs_pma" version="*" 
ip_interface="gtrefclk_in">
      <associated_board_interfaces>
  <associated_board_interface name="sgmii_mgt_clk" order="1"/> 
  <associated_board_interface name="sma_mgt_clk" order="0"/> 
      </associated_board_interfaces>
    </ip>
  </ip_associated_rule>
</ip_associated_rules>