IP Board Awareness - 2023.1 English

Vivado Design Suite User Guide: System-Level Design Entry (UG895)

Document ID
UG895
Release Date
2023-05-16
Version
2023.1 English

For AMD target reference platforms or evaluation boards, IP has knowledge of the FPGA pins that are used on the target boards. This is called board awareness. Based on that information, the IP integrator board/connection automation feature can assist you in tying the IP interfaces/ports to external ports on the board. IP integrator then creates the appropriate physical constraints and other I/O constraints required for the I/O port in question.

Current list of IPs that are board aware:

  • axi_emc_v3_0
  • axi_ethernet_buffer_v2_0
  • axi_ethernet_v7_2
  • axi_ethernetlite_v3_0
  • axi_gpio_v2_0
  • axi_iic_v2_1
  • axi_noc_v1_0
  • axi_pcie3_v3_0
  • axi_quad_spi_v3_2
  • axi_uart16550_v2_0
  • axi_uartlite_v2_0
  • clk_gen_sim_v1_0
  • clk_wiz_v5_4
  • clk_wiz_v6_0
  • clk_wizard_v1_0
  • cmac_usplus_v3_1
  • cmac_v2_6
  • ddr3_v1_4
  • ddr4_pl_v1_0
  • ddr4_v2_2
  • ethernet_1_10_25g_v2_7
  • gig_ethernet_pcs_pma_v16_2
  • i2s_receiver_v1_0
  • i2s_transmitter_v1_0
  • interlaken_v2_4
  • iomodule_v3_1
  • l_ethernet_v3_2
  • microblaze_mcs_v2_3
  • microblaze_mcs_v3_0
  • mig_7series_v4_2
  • mipi_csi2_rx_subsystem_v5_1
  • mipi_dphy_v4_3
  • mipi_dsi_tx_subsystem_v2_2
  • mrmac_v1_6
  • pcie4_uscale_plus_v1_3
  • pcie4c_uscale_plus_v1_0
  • pcie_3port_switch_v1_0
  • pcie_dma_versal_v2_0
  • pcie_versal_v1_0
  • proc_sys_reset_v5_0
  • qdma_v4_0
  • system_management_wiz_v1_3
  • tmr_comparator_v1_0
  • tmr_sem_v1_0
  • tmr_voter_v1_0
  • tri_mode_ethernet_mac_v9_0
  • tsn_temac_v1_0
  • usxgmii_v1_2
  • vcu_ddr4_controller_v1_1
  • versal_cips_v3_2
  • xdma_v4_1
  • xxv_ethernet_v4_0
Note: The IPs in the list are board aware for one or more boards based on the BOARD.ASSOCIATED_PARAM parameter of the IP's component.xml on every target board.