BUFG - 2023.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2023-05-17
Version
2023.1 English

Primitive: General Clock Buffer

  • PRIMITIVE_GROUP: CLOCK
  • PRIMITIVE_SUBGROUP: BUFFER
  • Families: UltraScale, UltraScale+

Introduction

This design element is a high-fanout buffer that connects signals to the global routing resources for low-skew distribution of the signal. BUFGs are typically used on clock nets as well other high-fanout nets like sets, resets, and clock enables.

Port Descriptions

Port Direction Width Function
I Input 1 Clock input.
O Output 1 Clock output.

Design Entry Method

Instantiation Yes
Inference Recommended
IP and IP Integrator Catalog No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- BUFG: General Clock Buffer
--       UltraScale
-- Xilinx HDL Language Template, version 2023.1

BUFG_inst : BUFG
port map (
   O => O, -- 1-bit output: Clock output.
   I => I  -- 1-bit input: Clock input.
);

-- End of BUFG_inst instantiation

Verilog Instantiation Template


// BUFG: General Clock Buffer
//       UltraScale
// Xilinx HDL Language Template, version 2023.1

BUFG BUFG_inst (
   .O(O), // 1-bit output: Clock output.
   .I(I)  // 1-bit input: Clock input.
);

// End of BUFG_inst instantiation

Related Information

  • UltraScale Architecture Clocking Resources User Guide (UG572)