BUFG_GT_SYNC - 2023.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2023-05-17
Version
2023.1 English

Primitive: Synchronizer for BUFG_GT Control Signals

  • PRIMITIVE_GROUP: CLOCK
  • PRIMITIVE_SUBGROUP: CLOCK_SYNC
  • Families: UltraScale, UltraScale+

Introduction

Synchronizer for the BUFG_GT CE and CLR functions.

Port Descriptions

Port Direction Width Function
CE Input 1 Asynchronous enable.
CESYNC Output 1 CE signal synchronized to CLK.
CLK Input 1 Clock.
CLR Input 1 Asynchronous clear.
CLRSYNC Output 1 CLR signal synchronized to CLK.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog Recommended

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- BUFG_GT_SYNC: Synchronizer for BUFG_GT Control Signals
--               UltraScale
-- Xilinx HDL Language Template, version 2023.1

BUFG_GT_SYNC_inst : BUFG_GT_SYNC
port map (
   CESYNC => CESYNC,   -- 1-bit output: Synchronized CE
   CLRSYNC => CLRSYNC, -- 1-bit output: Synchronized CLR
   CE => CE,           -- 1-bit input: Asynchronous enable
   CLK => CLK,         -- 1-bit input: Clock
   CLR => CLR          -- 1-bit input: Asynchronous clear
);

-- End of BUFG_GT_SYNC_inst instantiation

Verilog Instantiation Template


// BUFG_GT_SYNC: Synchronizer for BUFG_GT Control Signals
//               UltraScale
// Xilinx HDL Language Template, version 2023.1

BUFG_GT_SYNC BUFG_GT_SYNC_inst (
   .CESYNC(CESYNC),   // 1-bit output: Synchronized CE
   .CLRSYNC(CLRSYNC), // 1-bit output: Synchronized CLR
   .CE(CE),           // 1-bit input: Asynchronous enable
   .CLK(CLK),         // 1-bit input: Clock
   .CLR(CLR)          // 1-bit input: Asynchronous clear
);

// End of BUFG_GT_SYNC_inst instantiation

Related Information

  • UltraScale Architecture Clocking Resources User Guide (UG572)
  • UltraScale Architecture GTH Transceivers User Guide (UG576)