FDSE - 2023.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2023-05-17
Version
2023.1 English

Primitive: D Flip-Flop with Clock Enable and Synchronous Set

  • PRIMITIVE_GROUP: REGISTER
  • PRIMITIVE_SUBGROUP: SDR
  • Families: UltraScale, UltraScale+

Introduction

This design element is a single D-type flip-flop with clock enable and synchronous set.

  • When clock enable (CE) is High and synchronous set (S) is not asserted, the data on the data input (D) of this design element is transferred to the corresponding data output (Q) during the clock (C) transition.
  • When S is active, it overrides all other inputs and sets the data output (Q) High upon the next clock transition.
  • When CE is Low, clock transitions are ignored.
This flip-flop is asynchronously initialized when power is applied. When global set/reset (GSR) is active upon power-up or when GSR is asserted via the STARTUP block, the value of the INIT attribute is placed on the register's output.

Logic Table

Inputs Outputs
S CE D C Q
1 X X 1
0 0 X X No Change
0 1 D D

Port Descriptions

Port Direction Width Function
C Input 1 Clock input. Polarity is determined by the IS_C_INVERTED attribute.
CE Input 1 Active-High register clock enable.
D Input 1 Data input
Q Output 1 Data output
S Input 1 Synchronous set. Polarity is determined by the IS_S_INVERTED attribute.

Design Entry Method

Instantiation Yes
Inference Recommended
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
INIT BINARY 1'b1, 1'b0 1'b1 Sets the initial value of Q output after configuration or when GSR is asserted.
Programmable Inversion Attributes: Specifies whether or not to use the optional inversion on specific pins for this component to change the active polarity of the pin function. When set to 1 on a clock pin (C), it creates a negative edge register. When set to 1 on other pins, it changes the function to behave active-Low rather than active-High. If an external inverter is specified on one of these associated pins, the Vivado Design Suite will automatically set this attribute during the opt_design stage so that additional logic is not necessary for changing the input polarity.
IS_C_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion for the C pin of this component.
IS_D_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion for the D pin of this component. Must be set to 0 unless used as an I/O register.
IS_S_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion for the S pin of this component.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- FDSE: D Flip-Flop with Clock Enable and Synchronous Set
--       UltraScale
-- Xilinx HDL Language Template, version 2023.1

FDSE_inst : FDSE
generic map (
   INIT => '1',          -- Initial value of register, '0', '1'
   -- Programmable Inversion Attributes: Specifies the use of the built-in programmable inversion
   IS_C_INVERTED => '0', -- Optional inversion for C
   IS_D_INVERTED => '0', -- Optional inversion for D
   IS_S_INVERTED => '0'  -- Optional inversion for S
)
port map (
   Q => Q,   -- 1-bit output: Data
   C => C,   -- 1-bit input: Clock
   CE => CE, -- 1-bit input: Clock enable
   D => D,   -- 1-bit input: Data
   S => S    -- 1-bit input: Synchronous set
);

-- End of FDSE_inst instantiation

Verilog Instantiation Template


// FDSE: D Flip-Flop with Clock Enable and Synchronous Set
//       UltraScale
// Xilinx HDL Language Template, version 2023.1

FDSE #(
   .INIT(1'b1),          // Initial value of register, 1'b0, 1'b1
   // Programmable Inversion Attributes: Specifies the use of the built-in programmable inversion
   .IS_C_INVERTED(1'b0), // Optional inversion for C
   .IS_D_INVERTED(1'b0), // Optional inversion for D
   .IS_S_INVERTED(1'b0)  // Optional inversion for S
)
FDSE_inst (
   .Q(Q),   // 1-bit output: Data
   .C(C),   // 1-bit input: Clock
   .CE(CE), // 1-bit input: Clock enable
   .D(D),   // 1-bit input: Data
   .S(S)    // 1-bit input: Synchronous set
);

// End of FDSE_inst instantiation

Related Information

  • UltraScale Architecture Configurable Logic Block User Guide (UG574)