IBUFDS_DPHY - 2023.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2023-05-17
Version
2023.1 English

Primitive: Differential Input Buffer with MIPI support

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: INPUT_BUFFER
  • Families: UltraScale+

Introduction

Differential input buffer with MIPI support.

Port Descriptions

Port Direction Width Function
HSRX_DISABLE Input 1 Disable control for HS mode.
HSRX_O Output 1 HS RX output.
I Input 1 Data input0 PAD.
IB Input 1 Data input1 PAD.
LPRX_DISABLE Input 1 Disable control for LP mode.
LPRX_O_N Output 1 LP RX output (Slave).
LPRX_O_P Output 1 LP RX output (Master).

Design Entry Method

Instantiation Recommended
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
DIFF_TERM BOOLEAN TRUE, FALSE TRUE Turns the built-in differential termination on (TRUE) or off (FALSE).
IOSTANDARD STRING String "DEFAULT" Assigns an I/O standard to the element.
SIM_DEVICE STRING "7SERIES", "ULTRASCALE" "ULTRASCALE_PLUS" Set the device version.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- IBUFDS_DPHY: Differential Input Buffer with MIPI support
--              UltraScale
-- Xilinx HDL Language Template, version 2023.1

IBUFDS_DPHY_inst : IBUFDS_DPHY
generic map (
   DIFF_TERM => TRUE,               -- Differential termination
   IOSTANDARD => "DEFAULT",         -- I/O standard
   SIM_DEVICE => "ULTRASCALE_PLUS"  -- Set the device version (ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
                                    -- ULTRASCALE_PLUS_ES2)
)
port map (
   HSRX_O => HSRX_O,             -- 1-bit output: HS RX output
   LPRX_O_N => LPRX_O_N,         -- 1-bit output: LP RX output (Slave)
   LPRX_O_P => LPRX_O_P,         -- 1-bit output: LP RX output (Master)
   HSRX_DISABLE => HSRX_DISABLE, -- 1-bit input: Disable control for HS mode
   I => I,                       -- 1-bit input: Data input0 PAD
   IB => IB,                     -- 1-bit input: Data input1 PAD
   LPRX_DISABLE => LPRX_DISABLE  -- 1-bit input: Disable control for LP mode
);

-- End of IBUFDS_DPHY_inst instantiation

Verilog Instantiation Template


// IBUFDS_DPHY: Differential Input Buffer with MIPI support
//              UltraScale
// Xilinx HDL Language Template, version 2023.1

IBUFDS_DPHY #(
   .DIFF_TERM("TRUE"),             // Differential termination
   .IOSTANDARD("DEFAULT"),         // I/O standard
   .SIM_DEVICE("ULTRASCALE_PLUS")  // Set the device version (ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
                                   // ULTRASCALE_PLUS_ES2)
)
IBUFDS_DPHY_inst (
   .HSRX_O(HSRX_O),             // 1-bit output: HS RX output
   .LPRX_O_N(LPRX_O_N),         // 1-bit output: LP RX output (Slave)
   .LPRX_O_P(LPRX_O_P),         // 1-bit output: LP RX output (Master)
   .HSRX_DISABLE(HSRX_DISABLE), // 1-bit input: Disable control for HS mode
   .I(I),                       // 1-bit input: Data input0 PAD
   .IB(IB),                     // 1-bit input: Data input1 PAD
   .LPRX_DISABLE(LPRX_DISABLE)  // 1-bit input: Disable control for LP mode
);

// End of IBUFDS_DPHY_inst instantiation

Related Information

  • UltraScale Architecture SelectIO Resources User Guide (UG571)